Title :
A clock network of distributed ADPLLs using an asymmetric comparison strategy
Author :
Korniienko, A. ; Colinet, E. ; Scorletti, G. ; Blanco, E. ; Galayko, D. ; Juillard, J.
Author_Institution :
CEA, MINATEC, Grenoble, France
fDate :
May 30 2010-June 2 2010
Abstract :
In this paper, we describe an architecture of a distributed ADPLL (All Digital Phase Lock Loop) network based on bang-bang phase detectors that are interconnected asymmetrically. It allows an automatic selection between two operating modes (uni- and bidirectional) to avoid mode-locking phenomenon, to accelerate the network convergence and to improve the robustness to possible network failures in comparison to simple unidirectional mode.
Keywords :
clocks; digital phase locked loops; phase detectors; asymmetric comparison strategy; bang-bang phase detector; clock network; distributed all digital phase lock loop network; network convergence; Clocks; Convergence; Detectors; Energy consumption; Feedback loop; Frequency synchronization; Integrated circuit interconnections; Phase detection; Phase locked loops; Robustness;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537932
