A 1-change-in-4 delay-insensitive interchip link

We present a 1-change-in-4 (1c4) link for interchip communication that extends level-encoded dual-rail (LEDR). LEDR transmits a bit on every transition by using all four 2bit codewords, with the bit encoded by the current codeword (level-encoding) rather than the difference between it and the previous codeword (transition signaling). 1c4 transmits two bits on every transition by using all sixteen 4-bit codewords, preserving LEDR´s level-encoding property. Delay-insensitive I/O pad implementations for 1c4 encoding and decoding are described. Measurements of this chip-to-chip link, fabricated in a 0.18μm CMOS process, yielded a peak data-rate of 315 Mb/s at 1.8V and an energy efficiency of 89.8pJ/bit.