DocumentCode
3390233
Title
Effect of MOSFET gate-to-drain parasitic capacitance on class-E power amplifier
Author
Wei, Xiuqin ; Sekiya, Hiroo ; Kuroiwa, Shingo ; Suetsugu, Tadashi ; Kazimierczuk, Marian K.
Author_Institution
Grad. Sch. of Adv. Integration Sci., Chiba Univ., Chiba, Japan
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
3200
Lastpage
3203
Abstract
In this paper, we present analytical expressions for the waveforms and design equations for achieving the ZVS/ZDS conditions in the class-E power amplifier, taking into account the gate-to-drain parasitic capacitance of the MOSFET. We also give a design example along with PSpice simulation and experimental results. The voltage waveforms obtained from both the PSpice simulation and the circuit experiment achieved the class-E ZVS/ZDS conditions completely, which verify the analytical expressions. The results in this paper indicate that it is important to consider the effect of the MOSFET gate-to-drain capacitance for achieving the class E ZVS/ZDS conditions. The experimental power conversion efficiency achieved 92.8 % at output power Po = 4.06 W and operating frequency f = 7 MHz.
Keywords
MOSFET; SPICE; power amplifiers; zero voltage switching; MOSFET gate-to-drain parasitic capacitance; PSpice simulation; ZVS/ZDS conditions; class-E power amplifier; Analytical models; Circuit simulation; Frequency conversion; MOSFET circuits; Parasitic capacitance; Power MOSFET; Power amplifiers; Power conversion; Power generation; Zero voltage switching; Class-E power amplifier; MOSFET gate-to-drain capacitance; class-E ZVS/ZDS conditions; high efficiency; power conversion efficiency;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5537946
Filename
5537946
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