Title :
Development of dynamic tool PID/PWP limits to achieve product defect density goal
Author :
Jacobson, Lee ; Su, Hua
Author_Institution :
Nat. Semicond. Corp., South Portland, ME, USA
Abstract :
Summary form only given. Prediction of integrated circuit manufacturing yield has become the main application of developed yield models. In this paper, a different application, which is to develop tool PID/PWP limits to achieve product defect density goal, is shown. The developed limits are dynamic as most elements, such as defect size distribution, killer pareto and kill ratio change and improve from time to time. This method can be used to monitor any product yield enhancement activity in a consistent manner
Keywords :
circuit optimisation; inspection; integrated circuit modelling; integrated circuit yield; probability; defect size distribution; dynamic tool PID/PWP limits; integrated circuit manufacturing yield; kill ratio; killer pareto; product defect density goal; yield enhancement activity; yield models; Data analysis; Data mining; Inspection; Integrated circuit manufacture; Integrated circuit modeling; Integrated circuit yield; Jacobian matrices; Manufacturing processes; Predictive models; Semiconductor device manufacture;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE/SEMI
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-4050-7
DOI :
10.1109/ASMC.1997.630722
