Title :
A 1.31mW 38GHz frequency divider in 90 nm CMOS technology
Author :
Ting, Guo ; Li, Zhiqun ; Qin, Li
Author_Institution :
Sch. of Integrated Circuits, Southeast Univ., Nanjing, China
Abstract :
In this paper, a high speed broadband divide-by-2 frequency divider is presented. The proposed divider is mainly a source-coupled logic (SCL) structure formed with two dynamic-loading master-slave D latches, which enables high frequency operation, low power consumption and high input sensitivity. This divider exhibits wide locking range from 8GHz~38GHz and dissipates 1.31mW@38GHz from a 1.2V supply. The input sensitivity is only 4mV@16GHz. This chip occupies 685μm×430μm area with two on-chip spiral inductors in IBM 90nm CMOS process.
Keywords :
CMOS logic circuits; field effect MIMIC; flip-flops; frequency dividers; CMOS technology; IBM CMOS process; SCL structure; dynamic-loading master-slave D latches; frequency 8 GHz to 38 GHz; high-speed broadband divide-by-2 frequency divider; on-chip spiral inductors; power 1.31 mW; size 90 nm; source-coupled logic structure; voltage 1.2 V; CMOS integrated circuits; Frequency conversion; Latches; Power demand; Resistance; Sensitivity; Vehicle dynamics;
Conference_Titel :
Communication Technology (ICCT), 2011 IEEE 13th International Conference on
Conference_Location :
Jinan
Print_ISBN :
978-1-61284-306-3
DOI :
10.1109/ICCT.2011.6158047
