An improved high speed charge pump in 90 nm CMOS technology

Author

Chen, Sheng ; Li, Zhiqun ; Li, Qin

Author_Institution

Inst. of RF & OE ICs, Southeast Univ., Nanjing, China

fYear

2011

fDate

25-28 Sept. 2011

Firstpage

1095

Lastpage

1098

Abstract

This paper proposes an improved current steering charge pump in high speed application in IBM 90 nm technology. By using the current compensation circuit and accelerating acquisition circuit, the output voltage range with current matching is obviously enlarged. Simulation result shows that the charge pump can be applied for 500MHz frequency, with 1.4mW power consumption. Moreover, the current mismatch ratio of charge pump is less than 0.01% with output voltage swinging from 0.1 to 1.1V, very suitable for high speed PLL application.

Keywords

CMOS analogue integrated circuits; charge pump circuits; compensation; phase locked loops; CMOS technology; IBM technology; accelerating acquisition circuit; current compensation circuit; current matching; current mismatch ratio; frequency 500 MHz; high-speed PLL application; improved current steering charge pump; improved high-speed charge pump; power 1.4 mW; power consumption; size 90 nm; voltage 0.1 V to 1.1 V; voltage swinging; Acceleration; Charge pumps; Clocks; Feeds; MOSFET circuits; Mirrors; Phase locked loops; 0.01%; 500MHz; High speed; accelerating acquisition; current compensation;

fLanguage

English

Publisher

ieee

Conference_Titel

Communication Technology (ICCT), 2011 IEEE 13th International Conference on

Conference_Location

Jinan

Print_ISBN

978-1-61284-306-3

Type

conf

DOI

10.1109/ICCT.2011.6158051

Filename

6158051