Evaluation of final test process in 64-Mbit DRAM manufacturing system through simulation analysis

Author

Nakamae, Koji ; Ikeda, Hiroshi ; Fujioka, Hiromu

Author_Institution

Dept. of Inf. Syst. Eng., Osaka Univ., Japan

fYear

2003

fDate

31 March-1 April 2003

Firstpage

202

Lastpage

207

Abstract

We have evaluated the final test process in a 64-Mbit DRAM manufacturing system through an event-driven simulation analysis concerning the number of chips simultaneously tested by a memory test system. Four test flows for DRAMS and SDRAMs are considered. The overall number of planned production chips during a month is 3 million. The number of chips simultaneously tested is 32, 64, 128, and 256. Simulations for six months were carried out as a function of number of memory test systems by using parameter values extracted from a real final test facility in Japan. From the overall assessments as to the average TAT and the cost per chip, the final test facility should have 14 memory test systems for this production plan where 128 chips are simultaneously tested.

Keywords

DRAM chips; VLSI; integrated circuit manufacture; integrated circuit testing; production testing; 64 Mbit; DRAM manufacturing system; DRAM testing; SDRAM testing; event-driven simulation analysis; final test process evaluation; memory test system; simulation analysis; Analytical models; Costs; Discrete event simulation; Magnetic heads; Manufacturing systems; Modeling; Production; Random access memory; System testing; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI

ISSN

1078-8743

Print_ISBN

0-7803-7681-1

Type

conf

DOI

10.1109/ASMC.2003.1194493

Filename

1194493