Design of an optimal test pattern generator for built-in self testing of path delay faults

Author

Das, Debesh K. ; Chaudhuri, Indrajit ; Bhattacharya, Bhargab B.

Author_Institution

Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India

fYear

1998

fDate

4-7 Jan 1998

Firstpage

205

Lastpage

210

Abstract

A novel design of a test pattern generator (TPG) for built-in self-testing (BIST) of path delay faults, is proposed. For an n-input CUT, the TPG generates a sequence of length (n.2ⁿ+1), that includes all n.2ⁿ single-input-change (SIC) test pairs, and hence optimal. The generation of such a sequence of minimum length (i.e., n.2ⁿ+1) was an open problem. A simple iterative circuit of the TPG is then constructed. This provides minimum test application time for testing path delay faults, and compares favorably with the earlier BIST designs

Keywords

VLSI; built-in self test; delays; digital integrated circuits; integrated circuit testing; integrated logic circuits; logic design; logic testing; BIST; built-in self testing; iterative circuit; minimum test application time; optimal test pattern generator; path delay faults; sequence generation; single-input-change test pairs; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Robustness; Silicon carbide; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on

Conference_Location

Chennai

ISSN

1063-9667

Print_ISBN

0-8186-8224-8

Type

conf

DOI

10.1109/ICVD.1998.646603

Filename

646603