Impact of additional LDD rapid thermal annealing on submicron n-MOSFETs

Author

Wensheng, Qian ; Leong, V.K.W. ; Yuwen, Wang ; Yisuo, Li ; Mani, Pandey Shesh ; Manju, Sarkar ; Benistant, Francis ; Chu, Sanford

Author_Institution

Chartered Semicond. Manuf. Ltd., Singapore, Singapore

fYear

2003

fDate

31 March-1 April 2003

Firstpage

234

Lastpage

237

Abstract

An additional NLDD Rapid Thermal Annealing (RTA) had been implemented in thin-gate and thick-gate NMOS transistors. The threshold voltage (Vt) distribution at different gate lengths was investigated for devices with and without NLDD RTA. Lower roll-up and roll-off of Vt was observed with the inclusion of NLDD RTA. However, this observation only occurred for phosphorus-LDD NMOS devices rather than arsenic-LDD NMOS devices. Based on experimental results, TCAD tools was applied to analyze the removal of implant-induced damages by LDD RTA and to investigate the difference in channel profiles before and after LDD RTA. Finally, the mechanism of less Reverse Short Channel Effect and Short Channel Effect with LDD RTA was presented through TCAD simulation results.

Keywords

MOS integrated circuits; MOSFET; arsenic; boron; doping profiles; phosphorus; rapid thermal annealing; technology CAD (electronics); LDD RTA; Si:As; Si:P; TCAD tools; channel profiles; implant-induced damage; rapid thermal annealing; reverse short channel effect; submicron n-MOSFETs; thick-gate NMOS transistors; thin-gate NMOS transistors; threshold voltage distribution; Etching; Fluctuations; Implants; Impurities; MOS devices; MOSFET circuits; Rapid thermal annealing; Threshold voltage; Voltage measurement; Wood industry;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI

ISSN

1078-8743

Print_ISBN

0-7803-7681-1

Type

conf

DOI

10.1109/ASMC.2003.1194498

Filename

1194498