Some schemes for fast serial input multipliers

The design of fast multipliers for binary numbers represented in serial form is considered according to a general scheme composed by an array generator and a summator. The bits of the product are generated with the least delay with respect to the operators bits. The array generator computes the elements of the multiplier array. The summator computes the sum of the array elements in order to generate the product bits. The array elements can be generated according to two different general schemes: the first computes all the new array elements at each step (arranged on a diagonal and on a row of the multiplier array), the second computes the multiplier array elements column by column, Several schemes of array generators are given and compared, and for each of them a suitable summator using parallel counters is illustrated.