DocumentCode :
3390943
Title :
Optimizing logic design using Boolean transforms
Author :
Chavda, Pramit ; Jacob, James ; Agrawal, Vishwani D.
Author_Institution :
Tata-IBM, Bangalore, India
fYear :
1998
fDate :
4-7 Jan 1998
Firstpage :
218
Lastpage :
221
Abstract :
When a Boolean function is transformed by exclusive-OR with a suitably selected transform function, the new function is often synthesized with significantly reduced hardware. The transform function is separately synthesized and the original function is recovered as an exclusive-OR of the two functions. We select the transform to reduce the number of cubes in the function to be synthesized. The function is represented as a Shannon expansion about selected variables. A transform function is constructed such that a selected set of cofactors is complemented to minimize the overall number of cubes. Examples of single-output functions show an average area reduction of 19%. For a multiple-output function, transformations can be customized for each output
Keywords :
Boolean functions; circuit optimisation; integrated logic circuits; logic design; Boolean function; Boolean transforms; Shannon expansion; area reduction; cofactors; exclusive-OR; logic design; multiple-output functions; single-output functions; Boolean functions; Circuit synthesis; Delay; Design optimization; Hardware; Input variables; Jacobian matrices; Logic design; Logic functions; Network synthesis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
Conference_Location :
Chennai
ISSN :
1063-9667
Print_ISBN :
0-8186-8224-8
Type :
conf
DOI :
10.1109/ICVD.1998.646605
Filename :
646605
Link To Document :
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