Vector reduction methods for arithmetic pipelines

Vector reduction arithmetic accepts a vector as input and produces a scalar output. This class of vector operations forms the basis of many scientific computations. In a pipelined processor, a feedback loop is required to reduce vectors. Since the output of the pipeline depends on previous outputs, improper control of the feedback loop will destroy the benefit from pipelining. A generalized computing model is proposed to schedule the activities in a vector reduction pipeline. Two new vector reduction methods, symmetric and asymmetric, are proposed and analyzed for pipelined processing. These two methods compare favorably with the known recursive reduction method in achieving higher pipeline utilization and in eliminating large memory for intermediate results. An interleaving method is proposed to reduce multiple vectors to multiple scalars in a single arithmetic pipeline. The pipeline can be fully utilized by interleaved multiple vector processing.