An area-efficient VLSI architecture of the Viterbi decoder for reverse link IS-95 (CDMA) air interface

The IS-95 (North American CDMA) air interface standard specifies a constraint length K=9 and dual rate R=1/2 and R=1/3 convolutional encoder at the mobile transmitter (i.e., in the reverse link). This paper describes an area-efficient VLSI architecture of the Viterbi decoder at the base station receiver. We propose the use of offset binary representation in the branch metric calculator to achieve a 33% area reduction. We present an optimal state-sequential architecture for the add-compare-select engine which achieves maximum throughput for minimum area. A novel architecture is presented for the traceback unit, which is implemented as a block-circular buffer operating on the trellis in a sliding window fashion