DocumentCode
3391413
Title
INL based dynamic performance estimation for ADC BIST
Author
Duan, Jingbo ; Jin, Le ; Chen, Degang
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
3028
Lastpage
3031
Abstract
Data acquisition time and accurate instrumentation are the most significant contributors to ADC test cost. For most ADC products, static linearity (INL/DNL) test is required. This paper presents a methodology for estimating an ADC´s dynamic performance from its tested INL data, without requiring additional data acquisition or additional accurate sinusoidal sources. The tested INL(k) data is used to compute the power at harmonic frequencies and estimate ADC´s dynamic specifications such as THD and SFDR. Memory and computation requirement is very small comparing to that in traditional spectral testing. When combined with a BIST approach for INL testing, this method offers a very low cost BIST solution to ADC dynamic performance testing. Both simulation and experimental results show that the proposed method can estimate THD and SFDR values accurately.
Keywords
analogue-digital conversion; built-in self test; data acquisition; ADC BIST; ADC dynamic performance testing; ADC test cost; INL based dynamic performance estimation; INL testing; SFDR values; THD estimation; analog-to-digital converter; data acquisition time; harmonic frequency; spectral testing; static linearity test; Automatic testing; Built-in self-test; Circuit testing; Computational modeling; Costs; Data acquisition; Hardware; Linearity; Power system harmonics; Semiconductor device testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5538005
Filename
5538005
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