A 5-GHz fractional-N phase-locked loop with spur reduction technique in 0.13-μm CMOS

This work proposes a fractional phase error compensation approach for a classical fractional-N phase-locked loop (PLL) to reduce fractional spurs. The proposed corresponding-phase compensation technique incorporates a divider array and an auxiliary charge pump pair to overcome the fractional phase error. The main advantage of the proposed fractional-N PLL is that it only uses a constant compensation ratio when being a desired divide ratio. This PLL is fabricated in the TSMC 0.13-μm CMOS process. The total power consumption is about 17 mW. The measured results show that, with the proposed corresponding-phase compensation technique, the fractional spurs are reduced under classical fractional-N PLL.