Title :
A low-jitter supply-regulated charge pump phase-locked loop with built-in test and calibration
Author :
San-Um, Wimol ; Masayoshi, Tachibana
Author_Institution :
Electron. & Photonic Syst. Eng., Kochi Univ. of Technol., Kochi, Japan
fDate :
May 30 2010-June 2 2010
Abstract :
This paper presents a charge pump phase-locked loop with an integrated power supply regulation. Two independent regulators are employed in order to provide low-sensitivity supply voltages with inherent noise suppression for analog blocks, and to afford multiple reference voltages for test and calibration process. The built-in pre-screening test and calibration system based on the deviation of a control voltage during locking state facilitates on-chip accessibility and observability. Demonstrations of a 200-MHz charge pump phase-locked loop in 0.18-μm CMOS standard technology demonstrate low-jitter and low supply sensitivity performances with test and calibration functionality.
Keywords :
CMOS integrated circuits; built-in self test; calibration; phase locked loops; CMOS standard technology; analog blocks; built-in prescreening test; calibration process; frequency 100 MHz; inherent noise suppression; integrated power supply regulation; low supply sensitivity performances; low-jitter supply-regulated charge pump phase-locked loop; low-sensitivity supply voltages; multiple reference voltages; on-chip accessibility; on-chip observability; size 0.18 mum; Built-in self-test; CMOS technology; Calibration; Charge pumps; Control systems; Phase locked loops; Power supplies; Regulators; System testing; Voltage control; BIST; Calibration; Charge Pump PLL; Regulator;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5538019
