On-Line DA-LUT Architecture for High-Speed High-Order Digital FIR Filters

This paper presents a new architecture for distributed arithmetic look-up table (DALUT). The technique proposed here shows a dramatic improvement in the memory size of the architecture used for implementing a high-speed high-order digital finite impulse response filter. The architecture proposed in this paper provides DA technique the cure for its major disadvantage i.e. the exponential growth of the LUT as the filter order increase. Therefore, with this architecture, the LUT size is independent of the number of input variables. This is because the LUT contents are not precalculated before implementing the design, instead the only needed location contents are calculated while processing the input data. As a result of applying this architecture, the usual drawback of the FIR filters, i.e. high order needs when compared with their corresponding IIR filters is also vanished. Therefore, with this architecture we can easily design and implement FIR filters to meet the desired specifications even if the required filter order is high