A low-power VLSI implementation for variable block size motion estimation in H.264/AVC

Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This paper presents a low-power VLSI implementation for full-search VBSME. Compared to existing hardware architectures and implementations for VBSME, the proposed design employs a fast full-search block matching algorithm to reduce power consumption, while preserving the optimal solution and the throughput. The proposed architecture has been implemented and tested in Xilinx XtremeDSP Video Starter Kit Spartan-3ADSP 3400A Edition, and also verified using standard cell approach in UMC 0.18μm CMOS technology. Compared to other VBSME designs that give optimal solutions of Motion Vectors (MV), the proposed design can save power consumption by more than 56%.