DocumentCode :
3392318
Title :
On the performance of a hardware implementation of the wavelet transform
Author :
Walker, Shonda L. ; Foo, Simon Y. ; Petrone, Joseph
Author_Institution :
Dept. of Electr. & Comput. Eng., Florida Agric. & Mech. Univ., Tallahassee, FL, USA
fYear :
2003
fDate :
16-18 March 2003
Firstpage :
397
Lastpage :
399
Abstract :
This paper explores a hardware implementation of the wavelet transform using field programmable gate arrays (FPGA). Many signal processing applications use wavelets for more efficient signal decomposition than the traditional FFT technique. The parallel architectures of the FPGA are most suited to the practical filter bank implementations of the wavelets. Comparative hardware analyses show that wavelet transform outperforms the Fourier transform.
Keywords :
channel bank filters; digital filters; digital signal processing chips; field programmable gate arrays; parallel architectures; wavelet transforms; FPGA; comparative hardware analyses; field programmable gate arrays; filter bank; hardware implementation; parallel architectures; performance; signal decomposition; signal processing; wavelet transform; Array signal processing; Digital signal processing; Field programmable gate arrays; Filter bank; Fourier transforms; Hardware; Signal analysis; Signal processing algorithms; Wavelet analysis; Wavelet transforms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System Theory, 2003. Proceedings of the 35th Southeastern Symposium on
ISSN :
0094-2898
Print_ISBN :
0-7803-7697-8
Type :
conf
DOI :
10.1109/SSST.2003.1194599
Filename :
1194599
Link To Document :
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