A low-power VLSI architecture for the Viterbi decoder

This paper presents a VLSI architecture for the Viterbi decoder aimed at reducing the average power dissipation based on the modified T-algorithm and the radix-2 butterfly module. Simulation results show that on the average, more than half of states at each time stage are not needed to be processed for the (4, 1, 6) convolutional code at bit error probability P_b≤10^-2. Therefore, significant power reduction can be achieved by reducing the total number of path metric computations and eliminating waste memory read/write operations. Based on the TSMC 0.6 um SPDM process and the Compass cell library, the resulting core size is 2761×2996 μm².