Title :
Design of a modular chip for a reconfigurable artificial neural network
Author :
Plaskonos, P. ; Pakzad, S. ; Jin, B. ; Hurson, A.R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
This paper describes the design of the IBM fabricated basic neural unit (BNU) which can be used as a building block for a general-purpose reconfigurable artificial neural network (GRANNet). As a first step, a fully reconfigurable 2-BNU VLSI circuit is designed, implemented and tested. The hardware and software requirements of this implementation are presented. This paper also examines the issue of topological reconfigurability
Keywords :
VLSI; neural chips; neural nets; GRANNet; IBM fabricated basic neural unit; VLSI circuit; general-purpose reconfigurable artificial neural network; hardware; modular chip; reconfigurable artificial neural network; software; topological reconfigurability; Adders; Artificial neural networks; Circuit testing; Computer networks; Hardware; Integrated circuit interconnections; Neurons; Optical crosstalk; Optical interconnections; Very large scale integration;
Conference_Titel :
Developing and Managing Intelligent System Projects, 1993., IEEE International Conference on
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-3730-7
DOI :
10.1109/DMISP.1993.248636
