Title :
Faults test generation algorithm based on threshold for digital circuit
Author :
Liang Yingchun ; Yang Liyuan
Author_Institution :
Fac. of Electron. Inf. & Mech. Electr. Eng., Zhaoqing Univ., Zhaoqing, China
Abstract :
An effective test generation algorithm based on threshold for digital circuits is proposed in this paper. Firstly, threshold test generation model for digital circuit is constructed, acceptable faults can be distinguished from unacceptable faults by using the model. Then threshold test patterns can be generated for unacceptable faults by using mature stuck-at faults test generation algorithm. The experimental results on ISCAS´85 and ISCAS´89 circuits demonstrate the algorithm had high faults coverage and short test generation time.
Keywords :
circuit testing; fault diagnosis; ISCAS´85 circuits; ISCAS´89 circuits; digital circuit threshold; faults coverage; mature stuck-at faults test generation algorithm; test generation time; threshold test patterns; Circuit faults; Combinational circuits; Digital circuits; Educational institutions; Integrated circuit modeling; Large scale integration; Testing; acceptable faults; test generation algorithm; threshold test generation;
Conference_Titel :
Mechatronic Science, Electric Engineering and Computer (MEC), 2011 International Conference on
Conference_Location :
Jilin
Print_ISBN :
978-1-61284-719-1
DOI :
10.1109/MEC.2011.6025627
