Simple-VLIW: A fundamental VLIW architectural simulation platform

The very long instruction word (VLIW) architecture is considered to be one of the promising methods of increasing performance beyond standard reduced instruction set computing (RISC) architectures. However, few generally-accepted VLIW simulation environments are available for us in exploring the VLIW instruction set architectures (ISA) and their corresponding microarchitectures. Motivated by characterizing and evaluating VLIW-based designs more quickly and accurately, we present the design of a fundamental discrete-event driven software simulation platform, simple-VLIW, dedicated to VLIW architectures. The software decouples fast functional simulations and accurate cycle-based performance evaluations to provide different levels of details. With user-configurable parameters and driven by typical workloads, the simple-VLIW offers fast and accurate evaluations of VLIW-based architectures. It executes millions of instructions per second, and the results of which are consistent with our theoretical analysis very well. As a valuable tool, the proposed simulator can significantly expedite the research and the development of VLIW architectures.