• DocumentCode
    3393339
  • Title

    The input pattern order problem II: Evolution of multiple-output circuits in hardware

  • Author

    Trefzer, Martin A. ; Kuyucu, Tüze ; Miller, Julian F. ; Tyrrell, Andy M.

  • Author_Institution
    Dept. of Electron., Univ. of York, York
  • fYear
    2009
  • fDate
    April 30 2009-March 2 2009
  • Firstpage
    32
  • Lastpage
    38
  • Abstract
    It has been shown in previous work that the design of the input pattern plays and important role in intrinsic evolvable hardware. The results have shown that randomising the input pattern during the course of evolution is mandatory in order to achieve valid circuits that work correctly under all conditions. Furthermore, it was found that randomising the input pattern order helps evolution to avoid local optima. Due to the fact that it becomes exponentially more difficult to successfully evolve circuits with increasing number of outputs, this paper addresses the importance of the input pattern order problem (IPOP) for the second time, with a focus on the intrinsic evolution of digital circuits with multiple outputs. In this paper, we investigate whether it is also possible to design the input pattern in a way to improve the performance of evolution when tackling multiple output problems. A different approach to IPOP is taken, where input pattern order is used as a method of balancing the distribution of the output values. The aim is to equalise the fitness value range by using weighted input vectors in order to obtain a smoother search landscape for multiple output circuits. The proposed method is tested on the intrinsic evolution of 4-bit AND, 4-bit parity, 2-bit full adder, and 2-bit multiplier. Furthermore, the results for the intrinsically evolved multipliers are compared with software simulations in order to determine whether there is a benefit for both intrinsic and extrinsic evolution.
  • Keywords
    adders; logic gates; parity; 2-bit full adder; 4-bit AND; 4-bit parity; digital circuits; fitness value range equalissation; input pattern order problem; intrinsic evolvable hardware; intrinsically evolved multipliers; multiple-output circuits; search landscape; weighted input vectors; Adders; Circuit simulation; Circuit testing; Digital circuits; Hardware; Logic circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Evolvable and Adaptive Hardware, 2009. WEAH '09. IEEE Workshop on
  • Conference_Location
    Nashville, TN
  • Print_ISBN
    978-1-4244-2755-0
  • Type

    conf

  • DOI
    10.1109/WEAH.2009.4925665
  • Filename
    4925665