Title :
Top-down design of a high speed DCT architecture and implementation [video compression]
Author :
Li, Arthur T. ; Rizkalla, Maher E. ; Gundrun, H.C.
Author_Institution :
Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
This paper presents a high speed implementation of a 32 bit floating point discrete cosine transform, DCT, utilizing top-down approach. The VHDL code for the floating point adder/subtracter, multiplier, and shifter as building blocks for one dimensional DCT were successfully written and simulated and checked using test vectors that verified the design approach of the DCT. The circuit details the algorithm and results of simulation.
Keywords :
adders; data compression; discrete cosine transforms; floating point arithmetic; hardware description languages; multiplying circuits; video coding; VHDL code; design approach; floating point adder/subtracter; floating point discrete cosine transform; high speed DCT architecture; multiplier; test vectors; top-down design; Buildings; Circuit simulation; Circuit testing; Discrete cosine transforms; Fast Fourier transforms; Flow graphs; Image coding; Image storage; Transform coding; Video compression;
Conference_Titel :
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Print_ISBN :
0-7803-3694-1
DOI :
10.1109/MWSCAS.1997.662302
