Design techniques for gate-leakage reduction in CMOS circuits

Oxide tunneling current in MOS transistors is fast becoming a non-negligible component of power consumption, as gate oxides get thinner, and could become in the future the dominant leakage mechanism in sub-100 nm CMOS circuits. In this paper, we present an analysis of static CMOS circuits from a gate-leakage point of view. We first consider the dependence of the gate current on various conditions for a single transistor and identify 3 main regions in which a MOS transistor will operate between clock transitions. The amount of gate-current differs by several orders of magnitude from one region to another. Whether a transistor will leak significantly or not is determined by its position in relation to other transistors within a structure. By comparing logically equivalent but structurally different CMOS circuits, we find that the gate current exhibits a \´structure dependence\´. Also, the total gate-leakage in a given structure varies significantly for different combinations of inputs, from which we derive "state-dependent gate-leakage tables" that can be used to estimate the total amount of gate-current for a large circuit. Finally, we suggest guidelines aimed at reducing the amount of oxide-leakage current based on the presented structure and state dependencies.