DocumentCode :
3394420
Title :
Quantifying error in dynamic power estimation of CMOS circuits
Author :
Gupta, Puneet ; Kahng, Andrew B.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
fYear :
2003
fDate :
24-26 March 2003
Firstpage :
273
Lastpage :
278
Abstract :
Conventional power estimation techniques are prone to many sources of error. With increasing dominance of coupling capacitances, capacitive coupling potentially contributes significantly to UDSM power consumption. We analyze potential sources of inaccuracy in power estimation, focusing on those due to coupling. Our results suggest that traditional power estimates can be off by as much as 50%.
Keywords :
CMOS integrated circuits; error analysis; power consumption; CMOS circuits; UDSM power consumption; capacitive coupling; dynamic power estimation; power estimation; quantifying error; Capacitance; Circuit simulation; Computer errors; Coupling circuits; Crosstalk; Energy consumption; Frequency estimation; Integrated circuit interconnections; Switching circuits; Terminology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
Print_ISBN :
0-7695-1881-8
Type :
conf
DOI :
10.1109/ISQED.2003.1194745
Filename :
1194745
Link To Document :
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