Design and analysis of low-voltage current-mode logic buffers

Author

Heydari, Payam

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA

fYear

2003

fDate

24-26 March 2003

Firstpage

293

Lastpage

298

Abstract

This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a chain of tapered CML buffers is proposed. The differential architecture of a CML buffer makes it functionally robust in the presence of environmental noise sources (e.g., crosstalk, power/ground noise). The circuit design issues in regard to the CML buffer are compared with those in a conventional CMOS inverter. It is shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.

Keywords

CMOS logic circuits; buffer circuits; current-mode circuits; current-mode logic; integrated circuit design; logic design; CML buffers; CMOS inverters; analytical models; circuit design; crosstalk; differential architecture; environmental noise sources; functionally robust buffer; high speed low voltage applications; low voltage current-mode logic buffers; power/ground noise; Bandwidth; Circuits; Delay; Inverters; Logic design; Signal analysis; Signal design; Subthreshold current; Transconductance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on

Print_ISBN

0-7695-1881-8

Type

conf

DOI

10.1109/ISQED.2003.1194748

Filename

1194748