DocumentCode
3394568
Title
Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis
Author
Yang, Jae-Seok ; Kim, Jeong-Yeol ; Choi, Joon-Ho ; Yoo, Moon-Hyun ; Kong, Jeong-Taek
Author_Institution
Dept. of Device Solution Network, Samsung Electron., South Korea
fYear
2003
fDate
24-26 March 2003
Firstpage
344
Lastpage
347
Abstract
As the portion of coupling capacitance increases in smaller process geometries, accurate coupled noise analysis is becoming more important in current design methodologies. We propose a method to determine whether aggressors can potentially switch simultaneously with the victim or not. The functional information is used to classify the aggressors. Our functional pruning algorithm inspects the conflict of the net states using CNF (conjunction normal form) and BDD (binary decision diagram). We present the experimental results on several industrial circuits. In the experiments, 6.4% of total aggressors are false and the accuracy of delay calculation can be improved up to 36.6%.
Keywords
binary decision diagrams; crosstalk; delay estimation; integrated circuit noise; logic design; accurate coupled noise analysis; binary decision diagram; conjunction normal form; coupling capacitance; current design methodology; delay calculation; false aggressors; full chip crosstalk analysis; functional pruning algorithm; industrial circuits; net states; process geometry; Accuracy; Binary decision diagrams; Boolean functions; Capacitance; Circuits; Crosstalk; Data structures; Design methodology; Geometry; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
Print_ISBN
0-7695-1881-8
Type
conf
DOI
10.1109/ISQED.2003.1194756
Filename
1194756
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