Title :
PDL: a new physical synthesis methodology
Author :
Shibuya, Toshiyuki ; Murgai, Rajeev ; Kondo, Toshiaki ; Emi, Kazuhiro ; Kawamura, Kaoru
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. It provides a common database for delay calculation, logic optimization, placement, and routing tools so that they can work and interact closely. We present results on industrial circuits showing the efficacy of this methodology.
Keywords :
critical path analysis; delay estimation; integrated circuit design; integrated circuit layout; logic design; logic partitioning; network routing; optimisation; timing; PDL; common database; delay calculation; industrial circuits; layout quality; logic optimization; logic placement; optimality; physical synthesis methodology; routing tools; timing constraints; timing quality; Circuit synthesis; Delay estimation; Design optimization; Integrated circuit interconnections; Laboratories; Logic; Page description languages; Routing; Timing; Wires;
Conference_Titel :
Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
Print_ISBN :
0-7695-1881-8
DOI :
10.1109/ISQED.2003.1194757
