On-chip interconnect inductance - friend or foe

Author

Wong, S. Simon ; Yue, Patrick ; Chang, Richard ; Kim, So-Young ; Kleveland, Bendik ; O´Mahony, Frank

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

2003

fDate

24-26 March 2003

Firstpage

389

Lastpage

394

Abstract

Inductance associated with on-chip wires can no longer be ignored as chip operation frequencies increase into GHz regime. Because the magnetic field propagates a very long range, the extraction of wire inductance is not just dependent on the immediate neighboring environment. This paper discusses the various difficulties of extracting inductance of randomly placed wires in a typical chip environment. With dedicated return path, the wire inductance can be controlled and benefit the design of high-speed circuits. Specific examples are illustrated.

Keywords

high-speed integrated circuits; inductance; integrated circuit interconnections; 10 GHz; 16 GHz; 23 GHz; CMOS distributed amplifier; CMOS distributed oscillator; chip environment; chip operation frequencies; high speed circuits; magnetic field; on chip interconnect inductance; on chip wires; standing wave clock; wire inductance; Capacitance; Circuit simulation; Data mining; Frequency; Inductance; Integrated circuit interconnections; Magnetic fields; System-on-a-chip; Testing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on

Print_ISBN

0-7695-1881-8

Type

conf

DOI

10.1109/ISQED.2003.1194764

Filename

1194764