Analyzing internal-switching induced simultaneous switching noise

Author

Yang, Li ; Yuan, J.S.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Central Florida Univ., Orlando, FL, USA

fYear

2003

fDate

24-26 March 2003

Firstpage

410

Lastpage

415

Abstract

The internal-switching induced simultaneous switching noise (SSN) is studied in the paper. Unlike ground bounce caused by driving off-chip loading, both power-rail and ground-rail wire/pin impedances are important in evaluating internal SSN, and the double negative feedback mechanism should be accounted for. Based on the lumped-model analysis and taking into account the parasitic effects and velocity-saturation effect of MOS transistors, a novel analytical model is developed which includes both switching and non-switching gates. The proposed model is employed to analyze on-chip decoupling capacitance, wire/pin inductance effect and loading effect analytically. Good agreements with SPICE simulations are obtained for submicron technology.

Keywords

MOSFET; SPICE; capacitance; electric impedance; equivalent circuits; feedback; inductance; integrated circuit modelling; integrated circuit noise; lumped parameter networks; switching circuits; MOS transistors; SPICE simulations; driving off chip loading; equivalent switching circuit model; ground bounce; ground rail wire; internal switching; lumped model analysis; negative feedback; nonswitching gates; on chip decoupling capacitance; parasitic effects; pin impedances; power rail; simultaneous switching noise; submicron technology; switching; velocity saturation effect; Analytical models; Circuit noise; Circuit simulation; Impedance; Inductance; MOSFETs; Negative feedback; Rails; Switching circuits; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on

Print_ISBN

0-7695-1881-8

Type

conf

DOI

10.1109/ISQED.2003.1194768

Filename

1194768