Title :
A low power floating point accumulator
Author :
Pillai, R.V.K. ; Al-Khalili, D. ; Al-Khalili, A.J.
Author_Institution :
Concordia Univ., Montreal, Que., Canada
Abstract :
In CMOS logic implementations, the architectural/algorithmic power/delay/area implications of functional units are crucial as far as design economies of the target application are concerned. This paper addresses the architectural design of a low power floating point accumulator by using a transition activity scaled triple data path floating point adder core. The proposed scheme offers a worst case power reduction of 50% in comparison to schemes that use conventional floating point adders. The reduction in power delay product is better than 3X
Keywords :
CMOS logic circuits; adders; data flow computing; floating point arithmetic; CMOS logic implementations; architectural design; floating point adder core; low power floating point accumulator; power delay product reduction; transition activity scaled triple data path; Algorithm design and analysis; CMOS logic circuits; Computer architecture; Delay; Digital signal processing; Educational institutions; Energy consumption; Hardware; Logic design; Parallel processing;
Conference_Titel :
VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
Conference_Location :
Chennai
Print_ISBN :
0-8186-8224-8
DOI :
10.1109/ICVD.1998.646628
