DocumentCode :
3394815
Title :
Generation of hazard identification functions
Author :
Michael, Maria K. ; Tragoudas, Spyros
Author_Institution :
CSE Dept., Notre Dame Univ., IN, USA
fYear :
2003
fDate :
24-26 March 2003
Firstpage :
419
Lastpage :
424
Abstract :
We study the problem of identifying the complete set of pairs of input patterns that can cause different types of hazards to appear at a circuit line. A novel methodology to implicitly identify all possible input configurations is proposed. The technique is based on a systematic derivation of the conditions for the occurrence of static and dynamic hazards at a line, which are subsequently formulated as Boolean functions defined over variables representing the primary input signals. Our experimental results demonstrate that the proposed approach is very promising and outperforms existing approaches. In addition, they show that a proposed solution for the decision problem of hazard existence at a circuit line is very efficient.
Keywords :
Boolean functions; VLSI; binary decision diagrams; combinational circuits; identification; logic testing; timing; Boolean function; VLSI CAD; circuit line; combinational circuits; decision problem; dynamic hazard; hazard identification function; input pattern; primary input signals; single-input changes; static hazard; systematic derivation; Boolean functions; Circuit synthesis; Circuit testing; Combinational circuits; Delay; Hazards; Microwave integrated circuits; Sequential circuits; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on
Print_ISBN :
0-7695-1881-8
Type :
conf
DOI :
10.1109/ISQED.2003.1194769
Filename :
1194769
Link To Document :
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