Title :
90nm CMOS technology characterization at transfer and ramp
Author :
Kelleher, A. ; Gourley, D. ; Holmes, A.M. ; Hepburn, T. ; Farrell, C. ; Groves, R. ; Taskin, T. ; McMillan, J. ; Rawlins, W.
Author_Institution :
Intel Ireland Ltd, Leixlip, Ireland
Abstract :
This paper gives an overview of the matching and characterization requirements during the successful transfer and ramp of a high yielding 90 nm CMOS technology on 300 mm wafer size. In particular, the different characterization phases are examined and key aspects of achieving a high yielding technology during both transfer and ramp is discussed.
Keywords :
CMOS integrated circuits; integrated circuit measurement; integrated circuit yield; nanoelectronics; 300 mm; 90 nm; CMOS technology ramp; CMOS technology transfer; characterization requirements; high yielding technology; matching requirements; CMOS technology; Costs; Dielectric constant; Implants; Isolation technology; MOSFETs; Manufacturing processes; Power generation; Robustness; Space technology;
Conference_Titel :
Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on
Print_ISBN :
0-7803-8855-0
DOI :
10.1109/ICMTS.2005.1452208
