Enhanced high speed modular multiplier using karatsuba algorithm

High speed modular multiplier is a primary requirement of multi-core processors because of critical applications such as security and high performance, many of which requires efficient and reliable hardware implementations. The classical methods are developed using Barrett´s reduction and Montgomery multiplications. But the intermediate quotient is very large and main trade-off of this project is speed. To overcome this karatsuba multiplication is used to enhance the speed and potential of parallel processing. The result shows about the comparison of area and power of the existing algorithms. From the result our proposed method achieves high speed compared with other modular multipliers. The different type of algorithms developed as architectures and the digit serial basic concept is established to each algorithms. Also it is used to increase the potential achieve the parallel implementation. The proposed modular multiplier is done on the proposed architecture of digit serial multipliers using existing mathematical algorithms. This method reaches the maximum speed and hence the area gets reduced. Implementation of the proposed modular algorithm in this project have the less power consumption compared to their counterparts with similar modular algorithms.