Design and analysis of a TB/sec memory system

The design and analysis of a Terabyte per second (TB/sec) memory system is presented. The interface technology utilizes a bi-directional low-swing differential signaling with a data transfer rate of 16 Gbps/pair. The memory system uses asymmetrical architecture where the timing adjustment and equalization circuits for both memory WRITE and READ are on the controller to reduce the memory cost. This paper describes the design and analysis employed to develop the memory interface using conventional and low-cost interconnect technologies. The design and characterization of the prototype system at component and system-level are presented and model to hardware correlations are discussed at component and system levels. System analysis is used to optimize and predict the yield of the system, to calculate system timing and voltage margins, and to verify targeted bit-error-rate (BER).