On-chip bus signaling using passive compensation

Author

Zhang, Yulei ; Zhang, Ling ; Deutsch, Alina ; Katopis, George A. ; Dreps, Daniel M. ; Buckwalter, James F. ; Kuh, Ernest S. ; Cheng, Chung-Kuan

Author_Institution

ECE Dept., Univ. of California, San Diego, La Jolla, CA

fYear

2008

fDate

27-29 Oct. 2008

Firstpage

33

Lastpage

36

Abstract

A new scheme for bus signaling using on-chip lossy transmission lines with passive compensation is introduced in this paper to address the performance limitation brought by the scaling issues of on-chip global wires. The new scheme is designed and optimized based on eye-diagram prediction algorithm and sequential quadratic programming (SQP) flow. We perform a case study to demonstrate feasibility of the proposed scheme. The results show that, at 45 nm technology node, the new scheme achieves 20.58 ps/mm transmission speed and has the power efficiency of 0.106 pJ/bit considering the crosstalk effects.

Keywords

integrated circuit interconnections; quadratic programming; transmission lines; crosstalk effects; eye-diagram prediction algorithm; on-chip bus signaling; on-chip global wires; on-chip lossy transmission lines; passive compensation; power efficiency; sequential quadratic programming flow; size 45 nm; Crosstalk; Delay; Energy consumption; Integrated circuit interconnections; Power system interconnection; Quadratic programming; Repeaters; System-on-a-chip; Transceivers; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-2873-1

Type

conf

DOI

10.1109/EPEP.2008.4675869

Filename

4675869