DocumentCode :
3395626
Title :
An active crosstalk reduction technique for parallel high-speed links in low cost wirebond BGA packages
Author :
Hu, Yan ; Chen, Jikai ; Lamson, Michael ; Bashirullah, Rizwan
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL
fYear :
2008
fDate :
27-29 Oct. 2008
Firstpage :
37
Lastpage :
40
Abstract :
We report a 4-channel 8 Gb/s/channel transmitter test chip assembled in a low cost 4-layer wirebond BGA package to evaluate the impact of active cross-talk mitigation and equalization techniques on signal performance. A half-rate 4-tap feed-forward and a cross-talk induced jitter equalizer is used to compensate package interconnect losses and data dependent signal coupling, respectively. All coefficients of the FFE and crosstalk jitter equalizer have programmable polarity and magnitude. The chip power dissipation is 225 mW, or 7 mW/Gb/s. The FFE and jitter equalizer achieves a measured RMS jitter reduction of 7.5-ps for an improvement of 50%.
Keywords :
CMOS digital integrated circuits; ball grid arrays; equalisers; integrated circuit design; integrated circuit noise; CMOS digital integrated circuits; active crosstalk reduction; ball grid arrays; bit rate 8 Gbit/s; data dependent signal coupling; feed-forward equalizer; jitter equalizer; package interconnect losses; parallel high-speed links; power 225 mW; transmitter test chip; wirebond BGA packages; Assembly; Costs; Crosstalk; Equalizers; Feedforward systems; Jitter; Packaging; Power dissipation; Testing; Transmitters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2873-1
Type :
conf
DOI :
10.1109/EPEP.2008.4675870
Filename :
4675870
Link To Document :
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