Simple modeling expressions for substrate network of on-chip inductors

Author

Lai, Ivan C H ; Fujishima, Minoru

Author_Institution

Sch. of Frontier Sci., Tokyo Univ., Tokyo, Japan

fYear

2005

fDate

4-7 April 2005

Firstpage

113

Lastpage

118

Abstract

Simple monomial expressions to determine the values of the components in the substrate network of a new on-chip inductor model are proposed. The expressions are given in terms of geometry parameters to be useful for the physical design of the layout. We have evaluated the accuracy of our expressions with a 3D field solver as well as comparisons with measured results. Inductors were fabricated using a 0.35 mum CMOS process as well as a 0.15 mum silicon-on-insulator (SOI) process to extract the results. The comparisons show sufficient agreement between the inductance and quality factor (Q-factor) to be used in design. An amplifier using the inductor models was simulated for the demonstration to show the estimation improvement of the IP3 given by this proposed inductor model.

Keywords

CMOS integrated circuits; Q-factor; equivalent circuits; integrated circuit modelling; silicon-on-insulator; thin film inductors; 0.15 micron; 0.35 micron; 3D field solver; CMOS process; IP3 estimation; Q-factor; RFIC; SOI; amplifier simulation; inductor equivalent circuit model; inductor geometry parameters; monomial expression; on-chip inductor substrate network; on-chip spiral inductors; Circuit simulation; Coils; Eddy currents; Frequency; Inductance; Inductors; Network-on-a-chip; Q factor; Radiofrequency integrated circuits; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on

Conference_Location

Leuven

Print_ISBN

0-7803-8855-0

Type

conf

DOI

10.1109/ICMTS.2005.1452240

Filename

1452240