Title :
Placement of shorting vias for power integrity in multi-layered structures
Author :
Hsu, Ssu-Hsuan ; Cheng, Yung-Shou ; Guo, Wei-Da ; Cheng, Hung-Hsiang ; Wang, Chen-Chao ; Wu, Ruey-Beei
Author_Institution :
Dept. of Electr. Eng. & Grad. Inst. of Commun. Eng., Nat. Taiwan Univ., Taipei
Abstract :
The effect of the number of the shorting vias on the power integrity of multi-layered structures has been demonstrated in this paper. Following that, an empirical design rule for the fewest number of the shorting vias is proposed to maintain the original power integrity and reduce the cost at the same time. For validation, the design concept is also realized in a real package structure at last.
Keywords :
electronics packaging; interconnections; printed circuits; empirical design rule; multilayered packages; multilayered structures; package structure; power integrity; printed circuit boards; Capacitance; Dielectric constant; Equivalent circuits; Impedance; Inductance; Laboratories; Packaging; Power engineering and energy; Resonance; Resonant frequency;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2873-1
DOI :
10.1109/EPEP.2008.4675885
