Substrate isolation in 0.18um CMOS technology

Author

Rezvani, G. Ali ; Tao, Jon

Author_Institution

RF Micro Devices, San Jose, CA, USA

fYear

2005

fDate

4-7 April 2005

Firstpage

131

Lastpage

136

Abstract

Various methods of substrate isolation in a typical 0.18 μm CMOS process technology, with and without deep nwell (DNW), have been studied. Results are presented on the impacts of guard ring, substrate contact size and proximity, and DNW at various biases on isolation. |S21| is used as a measure of isolation. An N+ to Psub junction diode is used as both the source of noise injected into the substrate and as the sensor for noise pick up. It is shown that isolation based on DNW works well up to several Gigahertz, but at higher frequencies the impacts of P+ guard ring and DNW are about the same in reducing the substrate coupling. It is also shown that the impact of DNW on substrate isolation is comparable with published results for SOI.

Keywords

CMOS integrated circuits; S-parameters; coupled circuits; integrated circuit measurement; integrated circuit noise; isolation technology; mixed analogue-digital integrated circuits; radiofrequency integrated circuits; 0.18 micron; CMOS technology substrate isolation; DNW; RFIC; S21 isolation measure; SOI; deep n-well isolation; guard ring; junction diode noise source; noise pick up sensor; substrate contact size; substrate coupling reduction; substrate proximity; CMOS process; CMOS technology; Conductivity; Coupling circuits; Diodes; Isolation technology; Noise measurement; Radio frequency; Silicon; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on

Print_ISBN

0-7803-8855-0

Type

conf

DOI

10.1109/ICMTS.2005.1452244

Filename

1452244