Parameter variation on chip-level

Integrated MOSFET circuits fabricated in actual technologies are packed on several square millimetres of chip area. Circuit building blocks distributed over a chip have to achieve the same specifications. The circuit features depend on device parameters which vary not only on a global scale (i.e., wafer scale) or on a local scale (i.e., close-packed device pairs) but also on a chip-level scale. A concept for characterization of intra-die-statistics is discussed which closes the gap between process control monitoring and matching characterization.