DocumentCode :
3396287
Title :
Effectiveness of on-die decoupling capacitance in improving chip performance
Author :
Kantorovich, Isaac ; Houghton, Chris
Author_Institution :
Intel, Hudson, MA
fYear :
2008
fDate :
27-29 Oct. 2008
Firstpage :
165
Lastpage :
168
Abstract :
The paper discusses results of dynamic timing analysis of on-die data and clock synchronization in the presence of power supply noise and shows that chip Fmax performance is less sensitive to amount on-die decoupling capacitance Cdie than it has been conventionally expected. The reason is a positive effect of the clock distribution jitter that neutralizes a negative impact of elevated supply noise after Cdie reduction. The paper shows conditions under which maximum clock frequency Fmax can even increase when Cdie is reduced.
Keywords :
power supply circuits; synchronisation; timing; chip Fmax performance; clock synchronization; dynamic timing analysis; on-die data; on-die decoupling capacitance; power supply noise; Capacitance; Clocks; Delay effects; Frequency synchronization; Latches; Noise reduction; Performance analysis; Power supplies; Propagation delay; Timing jitter;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2873-1
Type :
conf
DOI :
10.1109/EPEP.2008.4675904
Filename :
4675904
Link To Document :
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