• DocumentCode
    3396580
  • Title

    Genetic algorithm based approach for integrated state assignment and flipflop selection in finite state machine synthesis

  • Author

    Chattopadhyay, S. ; Chaudhuri, P. Pal

  • Author_Institution
    Dept. of Comput. Sci. & Technol., Bengal Eng. Coll., Howrah, India
  • fYear
    1998
  • fDate
    4-7 Jan 1998
  • Firstpage
    522
  • Lastpage
    527
  • Abstract
    Current renewed emphasis for more aggressive logic designs with lesser area, delay, and power, demands exploration of alternative avenues that would lead to better designs, may be at the higher cost of computation. This paper explores the avenue of the Genetic Algorithm (GA) for a holistic view for synthesis of Finite State Machine (FSM). Two aspects-state assignment and choice of sequential elements-significantly affect the cost of the combinational logic synthesized for a FSM. While the state assignment strategies reported in the literature target a specific type of sequential element (generally, a D flip-flop), this paper chooses a combination of available flip-flops to yield the best result. Thus the problems of state assignment and flip-flop selection have been integrated into a single genetic algorithmic formulation. Exhaustive experimentation done on a large suite of benchmarks have established the fact that on the average this tool outperforms the two level state assignment algorithm NOVA by more than 300%. The quality of the solution obtained and the high rate of convergence has established the effectiveness of the GA in solving this particular NP-complete problem. Further, the inherent parallelism of GA makes the proposed scheme ideal for solving the problem in a multiprocessor environment
  • Keywords
    circuit CAD; convergence; finite state machines; flip-flops; genetic algorithms; high level synthesis; state assignment; CAD; FSM synthesis; NP-complete problem; combinational logic; convergence; finite state machine synthesis; flipflop selection; genetic algorithmic formulation; integrated state assignment; logic design; multiprocessor environment; sequential elements selection; Automata; Circuit synthesis; Costs; Delay; Educational institutions; Encoding; Flip-flops; Genetic algorithms; Logic design; Programmable logic arrays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
  • Conference_Location
    Chennai
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-8224-8
  • Type

    conf

  • DOI
    10.1109/ICVD.1998.646659
  • Filename
    646659