DocumentCode :
3396932
Title :
Fewest vias design for microstrip guard trace by using overlying dielectric
Author :
Cheng, Yung-Shou ; Guo, Wei-Da ; Shiue, Guang-Hwa ; Cheng, Hung-Hsiang ; Wang, Chen-Chao ; Ruey-Beei Wu
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
fYear :
2008
fDate :
27-29 Oct. 2008
Firstpage :
321
Lastpage :
324
Abstract :
The unwanted ringing noise owing to the resonance related to the spacing of shorting vias on microstrip guard traces might degrade the signal quality of adjacent interconnects. This paper proposes a novel design method to reduce the ringing noise by overlying a thin dielectric with higher dielectric constant onto the original microstrip substrate. It has the advantages of minimizing the required number of shorting vias and achieving less restricted circuit routing.
Keywords :
integrated circuit design; microstrip circuits; noise; permittivity; dielectric constant; fewest vias design; microstrip guard trace; microstrip substrate; overlying dielectric; ringing noise; Circuit noise; Degradation; Design methodology; Dielectric substrates; High-K gate dielectrics; Integrated circuit interconnections; Microstrip; Noise reduction; Resonance; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Performance of Electronic Packaging, 2008 IEEE-EPEP
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2873-1
Type :
conf
DOI :
10.1109/EPEP.2008.4675945
Filename :
4675945
Link To Document :
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