Interfacing to boundary scan chips for system level BIT

The author describes a system-level built-in test architecture and illustrates how system designers can interface to boundary (and other) scan devices on boards to facilitate line replaceable unit and system-level built-in test, online monitoring, and fault isolation using both serial and real-time techniques. He also shows how to bridge the protocol gaps between the various scan design devices (e.g. LSSD, boundary scan, and VHSIC) to arrive at an integrated built-in test and diagnostics strategy. It is concluded that the only way to achieve the fault detection and fault isolation requirements for the system is to design each card to be fully testable. Each designer could configure the circuit in any way desired and use any mix of components. The only rule is to have testability circuitry that can communicate with a standard testability bus interface on each card so that the system BIT (built-in-test) processor can perform its tasks