DocumentCode :
3397547
Title :
A design of time-optimum and register-number-minimum systolic convolver
Author :
Umeo, Hiroshi
Author_Institution :
Osaka Electro-Communication University Neyagawashi, Hatsucho, 18-8, 572, Japan
fYear :
1987
fDate :
18-21 May 1987
Firstpage :
5
Lastpage :
12
Abstract :
We present an optimum bit-parallel/word-sequential systolic convolver. Our design is the best one among the previous many convolvers in the sense that its optimality in time and space performances is simultaneously attained without augmenting any global control, broadcasting, preloading, and/or multi sequential or parallel I/O ports, which were allowed in most of the previous designs. As an application of our convolver we give a systolic polynomial divider which can compute the polynomial division in exactly n + 0(1) steps on [min (n−m, m)/2] + 0(1) systolic cells, for the division of any degree n polynomial by any degree m polynomial(n ≧ m).
Keywords :
Clocks; Convolvers; Pattern matching; Polynomials; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Arithmetic (ARITH), 1987 IEEE 8th Symposium on
Conference_Location :
Como, Italy
Print_ISBN :
0-8186-0774-2
Type :
conf
DOI :
10.1109/ARITH.1987.6158720
Filename :
6158720
Link To Document :
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