Title :
On-chip signature checking for embedded memories
Author :
Abdulla, M.F. ; Ravikumar, C.P. ; Kumar, Anshul
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India
Abstract :
The multiple on-chip signature checking architecture proposed by the authors previously is an effective BIST architecture for testing the functional units in modern VLSI circuits. It is characterized by low aliasing, low area overhead and low testing time. However, a straight forward application of this architecture in testing the embedded RAMs will result in excessive area overheads. In this paper the authors propose a scheme to apply this architecture to embedded static RAMs with no significant increase in area. The scheme is applicable to testing chips that have multiple embedded RAMs of various sizes (e.g., ASIC chips in telecommunication applications)
Keywords :
SRAM chips; VLSI; application specific integrated circuits; built-in self test; digital integrated circuits; integrated circuit testing; integrated memory circuits; logic testing; ASIC chips; BIST architecture; VLSI circuits; embedded SRAM; embedded memories; embedded static RAMs; on-chip signature checking; Automatic testing; Built-in self-test; Clocks; Compaction; Delay; Electronic mail; Fault detection; Random access memory; Read-write memory; Very large scale integration;
Conference_Titel :
VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
Conference_Location :
Chennai
Print_ISBN :
0-8186-8224-8
DOI :
10.1109/ICVD.1998.646664
