Title :
Gate usage strategies applied to BiCMOS sea-of-gates arrays
Author :
Duchene, Philippe P. ; Declercq, Michel J.
Author_Institution :
Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
Abstract :
A methodology for comparing CMOS and BiCMOS gate usage strategies is applied to gate delay optimization. Advanced strategies mixing simple and buffered CMOS and BiCMOS gate configurations are shown to be significantly superior, in terms of speed and density, to full-CMOS or full-BiCMOS strategies. For typical capacitance distributions, the speed advantage can be as high as 70% compared to a pure BiCMOS solution. A similar method can be used to minimize area or power dissipation. A BiCMOS sea-of-gates master, designed by using this method, is presented
Keywords :
BiCMOS integrated circuits; application specific integrated circuits; logic arrays; optimisation; BiCMOS; BiCMOS gate configurations; CMOS; area minimisation; buffered BiCMOS; buffered CMOS; capacitance distributions; density; full-BiCMOS strategies; gate delay optimization; gate usage strategies; mixed CMOS/BiCMOS gates; power minimisation; sea-of-gates arrays; speed; speed advantage; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Delay; Logic arrays; Logic gates; MOSFETs; Power dissipation; Power supplies; Voltage;
Conference_Titel :
Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-0620-1
DOI :
10.1109/MWSCAS.1991.251964
